Today, in smart power technology, high voltage CMOS (HVCMOS) and low voltage CMOS (LVCMOS) exist on a common wafer. Low voltage CMOS technology operates in the 1V to 5V power levels. HVCMOS technology operates between 20V to 120V power levels.
In high voltage CMOS (HVCMOS) technology, a concern is the interaction between the LDMOS transistors and the adjacent low voltage CMOS circuitry. In HVCMOS, inductive “load dumps” initiate injection of carriers into the chip substrate. As a result of the physical size of the HVCMOS and LDMOS devices, as well as the magnitude of the current injection, it is critical not to disturb the other chip functions on the smart power chips.
In addition, CMOS latchup is a growing issue in the smart power applications due to the harsh requirements of the automobile industry. CMOS latchup can occur from overshoot and undershoot phenomena. Other sources of issues for CMOS latchup include cable discharge events (CDE), transient oscillation events, and signal mis-match which can lead to injection of carriers into the substrate wafer.
Therefore, there is a need in smart power applications to isolate 120V operation from 45V operation, 120V operation from 5V operation, 120V operation from sub-5V operation, as well as 45V operation from 5V and sub-5V operation. Therefore, there is a need for a structure (and a method for forming the same) which electrically isolate each device from its neighbouring devices, where the neighbouring devices are at a different voltage level.
Today, system-on-chip (SOC) applications are also in the low voltage sector mixed signal (voltage) and radio frequency (RF) requirements. System-on-chip (SOC) applications has a wide range of power supply conditions, number of independent power domains, and circuit performance objectives. Different power domains are established between digital, analog and radio frequency (RF) functional blocks on an integrated chip. The integration of different circuits and system functions into a common chip has also resulted in solutions for ensuring that noise from one portion or circuit of the chip does not affect a different circuit within the chip. With the chip integration issues, the need for better guard rings and alternative guard ring solutions have had increased interest.